Non-volatile memory devices are capable of storing data even with the power is turned off. Depending on the technology, writing or erasing data in a non-volatile memory device may require that a current flows through a silicon oxide dielectric layer which can have a thickness of a few nanometers, so that an operating voltage of about 20 V and a programming time of microseconds may be necessary.
There has been suggested the use of a field-effect transistor having a semi-floating gate structure for use as a non-volatile memory element. Compared to a conventional floating gate transistor erase operation that is performed by applying a high voltage to control electron tunneling through the insulating dielectric layer, the semi-floating-gate transistor with a silicon body TFET quantum tunneling effect, and the use of pn junction diode, in which the operating voltage can be reduced to 2V, can have a single data erase and write operation time down to 1.3 nanoseconds. FIG. 1 is a cross-sectional view of a semi-floating gate transistor structure of the prior art.
FIGS. 2 to 7 shows cross-sectional views of intermediate stages of a method for manufacturing the semi-floating gate transistor structure of FIG. 1 according to the prior art. The prior art method may include the following steps:
At step S1′: an N-well region 101′ is formed in a substrate 100′, and a gate oxide layer 200′ is formed on a surface of N-well region 101′ and on a surface of substrate 100′, as shown in FIG. 2.
At step S2′; gate oxide layer 200′ and substrate 100′ are etched to form a groove 201′ in N-well region 101′, as shown in FIG. 3.
At step S3′: a P-type polycrystalline silicon layer (alternatively referred to as p-type polysilicon layer) is formed on gate oxide layer 200′ and filling groove 201′, as shown in FIG. 4. A pn junction diode is formed between the P-type polycrystalline silicon layer and the N-well region.
At step S4′; a portion of the p-type polysilicon layer 300′ is removed by etching, as shown in FIG. 5.
At step S5′: an ONO layer 400′ is formed on the P-type polysilicon layer, and an N-type polysilicon layer 500′ is formed on the ONO layer 400′, the gate oxide layer, and the N-well region 101′. The ONO layer 400′ is a stack of silicon oxide layer, a silicon nitride layer and a silicon oxide layer forming a layered structure.
At step S6′; N-type polysilicon layer 500′ and the ONO layer 400′ are sequentially removed by etching to form a structure, as shown in FIG. 7.
However, the above process steps of forming a groove further includes, after etching the gate oxide layer, etching the substrate, so that a portion of the floating gate electrode is formed in the substrate. Etching the substrate causes damage to the crystalline structure of the substrate, leading to an increase in the leakage current and power consumption of the semi-floating gate transistor device. Furthermore, the etching process and the lithographic minimum width capability determines the minimum feature size of the pn junction diode of the semi-floating gate device, and therefore, the above process is difficult to further reduce the size of the floating gate transistor. Moreover, when after the formation of the N-well region, the groove formed by etching, the boundary of N well region cannot be easily determined, and thus, the lithographic mask alignment accuracy is difficult to be determined, which may adversely affect the size of the channel. Therefore, it is difficult to form an effective pn junction diode. While such semi-floating-gate transistor structure provides the advantages of a fast erase time, but the size of the process using pn-junction diode formed as described above is greater than 0.5 microns, which makes it more difficult to apply a high degree of integration of semiconductor technology. Therefore, a technical solution of effectively improving data storage density with the continuous shrinkage in the size of a floating gate transistor with advances in semiconductor technology has become critical for the mass production of semiconductor devices.